1) Field of the Invention
The present invention relates to a data transfer control circuit in a system LSI (large-scale Integration).
2) Description of the Related Art
Japanese Patent Application Laid-Open No. 2001-229074 (0019–0023, FIG. 1) discloses an example of a data transfer control circuit in a system LSI. FIG. 10 is a block diagram of the data transfer control circuit disclosed in this publication.
The data transfer control circuit includes two bus masters, bus master-A 901 and bus master-B 902. The bus master-A 901 controls a master bus-A 903a, and the bus master-B 902 controls a master bus-B. 903b, to access a CPU (Central Processing Unit) (not shown) or the like connected to the master bus-A 903a and the master bus-B 903b, or an external device 911 that is a device outside of the LSI.
The master bus-A 903a and the master bus-B 903b have the same configuration. For example, the master bus-A 903a has an address signal bus 931 from which an address signal MADDR is transmitted, a control signal bus 932 from which a control signal is transmitted, a write data signal bus 933 from which data to be written by the bus master (hereinafter, “write data”) MDW is transmitted, and a read data signal bus 934 from which data read out from the external device 911 by the bus master (hereinafter, “read data”) MDR_E is transmitted.
A bus interface section 904 is connected to the master bus-A 903a and the master bus-B 903b. The bus interface section 904 performs conversion of a protocol of the master bus-A 903a and the master bus-B 903b when the bus master-B 902 accesses the external device 911 to a protocol of the external device 911.
Data holders 906 and 908, a data buffer 907, an external device controller 909, and an external address generator 910 are connected between the bus interface section 904 and the external device 911. The external address generator 910 is connected to the bus interface section 904 via an address signal bus 951, and also connected to the external device 911 via an address signal bus 961. The external device controller 909 is connected to the bus interface section 904 via a control signal bus 952, and also connected to the external device 911 via a control signal bus 962.
A read data output terminal of the data holder 908 is connected to the bus interface section 904 via a read data signal bus 953, and a read data input terminal is connected to a read data output terminal of the data buffer 907. A write data input terminal of the data holder 906 is connected to the bus interface section 904 via a write data signal bus 954, and a write data output terminal is connected to a write data input terminal of the data buffer 907. The read and write data input/output terminal of the data buffer 907 is connected to the external device 911 via a data signal bus 963.
The external device 911 is, for example, an SDRAM (Synchronous Dynamic Random Access Memory). The external address generator 910 generates an address signal of the external device 911 under control of the external device controller 909. The data buffer 907 fetches a write data signal held by the data holder 906 and outputs the signal to the external device 911 under control of the external device controller 909, and also fetches a read data signal output by the external device 911 and allows the signal to be held by the data holder 908.
The data read operation by the bus master-A 901 from the external device 911 will now be explained. The explanation of the data write operation for writing the data in the external device is omitted.
The whole of the address signal bus 951 through which an address signal EADDR is transmitted, the control signal bus 952 through which a control signal is transmitted, the read data signal bus 953 through which a read data signal EDR is transmitted, and the write data signal bus 954 through which a write data signal EDW is transmitted is referred to as an E bus 905. The signals transmitted to the respective buses are specified by using names of E bus address signal, E bus control signal, and E bus read signal, respectively.
The whole of the address signal bus 961 between the external address generator 910 and the external device 911, the control signal bus 962 between the external device controller 909 and the external device 911, and the data signal bus 963 between the data buffer 907 and the external device 911 is referred to as an external bus. The signals transmitted to the respective buses are specified by using names of an external bus address signal, an external bus control signal, and external bus read data signal.
The bus master-A 901 outputs a control signal necessary for performing data read to the control signal bus 932, and at the same time, also outputs the address signal MADDR of the external device 911 to be read to the address signal bus 931.
When the control signal for data read is output to the control signal bus 932, the bus interface section 904 confirms whether the address signal MADDR on the address signal bus 931 is the address signal to the external device 911. In this example, the address signal MADDR on the address signal bus 931 is an address signal to the external device 911, and hence the bus interface section 904 performs read operation of the external device 911 with respect to the E bus 905.
That is, the bus interface section 904 outputs the E bus control signal necessary for reading the external device 911 to the control signal bus 952, and at the same time, also outputs the E bus address signal EADDR for accessing the external device 911 to the address signal bus 951.
The external device controller 909 receives the E bus control signal from the control signal bus 952, generates an external bus control signal necessary for accessing the external device 911, and outputs the signal to the external device 911, and at the same time, also instructs the external device generator 910 to generate an address. Further, the external device controller 909 instructs the data buffer 907 to fetch the external bus read data signal.
When having received the E bus address signal EADDR from the bus interface section 904 in accordance with the instruction from the external device controller 909, the external address generator 910 generates an external bus address signal necessary for accessing the external device 911, and outputs the signal to the external device 911.
As a result, the external device 911 performs data read, using the external bus control signal and the external bus address signal. The external bus read data signal output by the external device 911 is input to the data holder 908 via the data buffer 907, temporarily held therein, transmitted as the E bus read data signal EDR to the read data signal bus 953 of the E bus 904, and as the read data signal MDR_E to the read data signal bus 934 in the master bus-A 903a through the bus interface section 904, and fetched by the bus master-A 901.
The timing of the data read operation is explained next, with reference to FIG. 11. FIG. 11 is a timing chart that explains the timing relation at the time of data read operation performed by the conventional data transfer control circuit. It is assumed that the external device 911 is the SDRAM.
FIG. 11 illustrates the items for the master bus, the E bus, and the external bus separately. The signals on the master bus include REQ, ACK, END, RW, MADDR, MDR_E, and MDW. REQ, ACK, END, and RW are the control signals to be transmitted onto the control signal bus 932. REQ is a bus access request signal, ACK is a bus access permission signal, END is a bus access end signal, and RW is a read/write signal. The other signals MADDR, MDR_E, and MDW have already been described above.
The signals on the E bus include EREQ, EEND, ERW, EADDR, EDR, and EDW. EREQ, EEND, and ERW are the E bus control signals to be transmitted onto the control signal bus 952. EREQ is an E bus access request signal, EEND is a bus access end signal, and ERW is an E bus read/write signal. The other signals EADDR, EDR, and EDW have already been described above.
The signals on the external bus include the control signal, address signal, and data signal. The external bus control signal includes a line activation command AC, an NOP (No-operation) command NP, a read command RD, and a bank deactivation command PR, and the SDRAM command is defined by the combination of these commands.
Referring to FIG. 11, at clock cycle “1”, the bus master-A 901 outputs the bus access request signal REQ “R0” to the master bus-A 903a, confirms the bus access permission signal ACK “R0”, and outputs the read/write signal RW and the address signal MADDR “R0”. To the read/write signal RW, a value “read” indicating that the bus access is the read access is output.
When the bus access request signal REQ “R0” is output, the bus interface section 904 reads the address signal MADDR “R0” to judge that it is an address with respect to the external device 911, and outputs the bus access permission signal ACK “R0” to the master bus-A 903a. 
The bus interface section 904 outputs the E bus access request signal EREQ “R1”, the E bus read/write ERW signal, and the E bus address signal EADDR “R0” to the E bus 905. To the E bus read/write signal ERW, a value “read” indicating that the E bus access is the read access is output.
The external device controller 909 receives the E bus access request signal EREQ “R1” from the bus interface section 904, and outputs a line activation command AC, an NOP command NP, a read command RD, and a bank deactivation command PR that are the external bus control signals necessary for accessing the SDRAM, in this order to the external device 911, synchronously to the respective clocks of clock cycles “1” to “5”.
The external address generator 910 receives the E bus address signal EADDR “R0” from the bus interface section 904, and outputs the external bus address signal necessary for accessing the SDRAM to the external device 911. In this case, the external address generator 910 time-divides the address into a row address “R0” and a column address “C0” and outputs these addresses. Specifically, the external address generator 910 generates the row address “R0” and the column address “C0” from the E bus address signal EADDR according to the external address generation instruction received from the external device controller 909. Then, the external address generator 910 outputs the row address “R0” at clock cycle “1” and the column address “C0” at clock cycle “3”.
Since it is assumed here that the CAS latency (Column Address Strobe Latency) of the SDRAM is two clocks, the read data signal “R0” read from the SDRAM at clock cycle “5” is input to the data buffer 907. The read data signal “R0” input to the data buffer 907 is taken into the data holder 908 under control of the external device controller 909 and temporarily held therein, and then output to the read data signal bus 953 of the E bus 905, as the E bus read data signal EDR “R0” at clock cycle “6”. The E bus read data signal EDR “R0” is output to the read data signal bus 934 of the master bus-A 903a as the read data signal MDR_E “R0” at the same clock cycle “6” through the bus interface section 904.
At this time, the bus interface section 904 outputs the bus access end signal END “R0” to the control signal bus 932 in the master bus-A 903a at the same clock cycle “6”. The bus master-A 901 reads this bus access end signal END “R0”, and fetches the read data signal MDR_E “R0” from the read data signal bus 934 in the master bus-A 903a. The bus interface section 904 outputs the E bus access end signal EEND “R1” to the external device controller 909 at the same clock cycle “6”.
With the second bus access, the external device controller 909 receives the E bus access request signal EREQ “R1” from the bus interface section 904, and outputs the line activation command AC, the NOP command NP, the read command RD, and the bank deactivation command PR that are the external bus control signals, to the external device 911 in this order, synchronously to the respective clocks of clock cycles “8” to “12”. Then, the external device controller 909 performs end processing at clock cycle “13”.
In this manner, in the conventional data transfer control circuit, the first bus access (SDRAM access) is performed, requiring six clock cycles (clock cycle “1” to “6”). The second bus access is performed in the same procedure, requiring six clock cycles (clock cycle “8” to “12”).
However, in the data transfer control circuit in the conventional system LSI, when accessing the external device, for example, an SDRAM, even when intermittently accessing continuous areas, the SDRAM must be deactivated temporarily, thereby causing a problem in that the bus use efficiency is bad.
Further, since the SDRAM is accessed every time there is a request from the bus master, if accesses concentrate, the bus bandwidth is not enough, thereby causing a problem in that the data transfer efficiency drops.